1. Field of the Invention
The present invention relates to an iterative concatenated code decoding circuit and an encoding/decoding system using the circuit. And more particularly relates to an iterative concatenated BCH (Bose-Chaudhuri-Hocquenghem) decoding circuit, in which two codes called the inner and outer code are concatenated.
2. Description of the Prior Art
The concatenated BCH (Bose-Chaudhuri-Hocquenghem) decoding circuit can improve the error correction capability by applying iterative decoding scheme, as shown in FIG. 12.
In FIG. 12, the input data Din is firstly encoded by an outer encoder 100. The encoded data Denc-outer is interleaved by an interleaver 200, and then encoded by an inner encoder 300. The encoded data Denc-inner output from the inner encoder 300 is output to a transmission path 400.
The encoded data Drev with the errors added through the transmission path 400 is decoded by an inner decoder 500, and the errors are corrected. The decoded data Ddec-inner is deinterleaved by a deinterleaver 600, and then decoded by an outer decoder 700, and the errors that are not corrected by the inner decoder 500 are corrected.
FIG. 13 is a block diagram showing the configuration of the conventional N-times iterative concatenated BCH decoder. The encoded data Drev received through the transmission path, not shown, is decoded by a first stage inner decoder 500-1. The decoded data Dinner-1 is deinterleaved by a first stage deinterleaver 600-1, and then decoded by a first stage outer decoder 700-1. The decoded data Douter-1 is interleaved again by a first stage interleaver 200-1, and then decoded by a second stage inner decoder 500-2.
The decoded data Dinner-2 is deinterleaved again by a second stage deinterleaver 600-2, and then decoded by a second stage outer decoder 700-2. The decoded data Douter-2 is interleaved again by a second stage interleaver 200-2. The above operation is iterated by N times to correct the transmission errors gradually.
FIG. 14 shows the configuration of the conventional BCH decoder. The BCH decoder comprises a syndrome calculating section 10, an error locator polynomial deriving section 20, an error location calculating section 30, a received code-word storing section 40, and an error correcting section 50.
To explain BCH decoding principle, BCH(255, 215) code is considered as an example. This code has 5 bits error correction capability per one code-word.
The syndrome calculating section 10 calculates the coefficients Si for a syndrome polynomial S(z) that is defined by the expression,S(z)=S1z+S2z2+ . . . +S10z10  (1)
The syndrome coefficients Si are defined by the expression,
                                                                        S                i                            =                              Y                ⁡                                  (                                      α                    i                                    )                                                                                                        =                                                Y                  0                                +                                                      Y                    1                                    ⁢                                      α                    i                                                  +                                                      Y                    2                                    ⁢                                      α                                          2                      ⁢                      i                                                                      +                                                      Y                    3                                    ⁢                                      α                                          3                      ⁢                      i                                                                      +                …                +                                                      Y                    254                                    ⁢                                      α                                          254                      ⁢                      i                                                                                                                                                              i                =                1                            ,              …              ⁢                                                          ,              5                                                          (        2        )            where Y(x) is a received polynomial and α is a primitive element.
Each coefficient of the received polynomial Y(x) corresponds to each bit of the encoded data Drev received through the transmission path. If the received polynomial Y(x) contains no error, the syndrome coefficients become all zero.
The error locator polynomial deriving section 20 derives an error locator polynomial σ(z), employing the Euclid's algorithm, and outputs it to the error location calculating section 30. The error locator polynomial σ(z) is represented by the expression,σ(z)=σ0+σ1z+ . . . +σ5z5  (3)
The error location calculating section 30 calculates an error location from the error locator polynomial.
The Chien search algorithm, which evaluates the error locator polynomial σ(z) at all field elements of GF(256) can be used to find error locations and values. If σ(αi) is a root of error locator polynomial σ(z), the power of the root indicates the error locations of the received code polynomial Y(x).
The error correcting section 50 corrects the received code-word stored in the received code-word storing section 40 on the basis of an error location input from the error location calculating section 30 and outputs the corrected code-word to the outside.
In the related-art techniques, the BCH code having the comparable coding ratio for the inner code and the outer code is employed. This BCH code was described in T. Mizuochi et al., “Transparent multiplexer featuring super FEC for optical Transport networking” (SubOptic 2001, P4.2.3, 2001) and Omar AIT SAB, “FEC contribution in submarine transmission systems” (SubOptic 2001, P4.2.6, 2001).
In the conventional iterative concatenated BCH decoding circuit as described above, if an average error number of the received code-word is greater than or equal to the number of correctable bits, the errors are hardly corrected with the BCH code. Since the outer decoder has a coding ratio comparable to that of the inner decoder, the outer decoder can hardly correct the errors when the inner decoder can hardly correct the errors.
Moreover, in the conventional iterative concatenated BCH decoder, the outer decoder and the inner decoder having the comparable coding ratio must be made the same circuit configuration, resulting in a problem that the circuit size becomes large. In particular, the circuit size is increased owing to the Euclid's algorithm or the Chien search algorithm.